View CY29351_936511.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY29351
2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
Features
* * * * * * * * * * * * * * Output frequency range: 25 MHz to 200 MHz Input frequency range: 25 MHz to 200 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 2.5% max Output duty cycle variation 9 Clock outputs: Drive up to 18 clock lines Two reference clock inputs: LVPECL or LVCMOS 150-ps max output-output skew Phase-locked loop (PLL) bypass mode Spread AwareTM Output enable/disable Pin-compatible with MPC9351 Industrial temperature range: -40C to +85C 32-Pin 1.0-mm TQFP package
Functional Description
The CY29351 is a low voltage high performance 200 MHz PLL-based zero delay buffer designed for high speed clock distribution applications. The CY29351 features LVPECL and LVCMOS reference clock inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Functional Table. These dividers allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS compatible output can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see the Table 1. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.
Block Diagram
Pin Configuration
REF_SEL
SELA PLL_EN
PLL_EN
VDDQB 27
TCLK
VSS
REF_SEL TCLK VCO 200 500 MHz
32
31
30
29
28
26
PECL_CLK
Phase Detector
/2 / /4
QA
25
VSS
QA
QB
LPF
/4 / /8
QB
FB_IN SELB SELC OE#
A VD D FB_IN SELA SELB SELC SELD A VSS PE CL_C LK
1 2 3 4 5 6 7 8
C Y29351
24 23 22 21 20 19 18 17
QC0 VD D Q C QC1 VS S QD0 VD D Q D QD1 VS S
10
11
12
13
14 QD3
15 VDDQD
/4 / /8
QC1
VDD QD4 VSS OE# PECL_CLK# QD2
/4 / /8 SELD
QD0 QD1 QD2 QD3 QD4
Cypress Semiconductor Corporation Document #: 38-07475 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134
16
QC0
9
* 408-943-2600 Revised July 26, 2004
CY29351
Pin Definitions[1]
Pin 8 9 30 28 26 22, 24 12, 14, 16, 18, 20 2 Name PECL_CLK TCLK QA QB QC(1,0) QD(4:0) FB_IN I/O I, PU I, PD O O O O I, PD Type LVPECL LVPECL Description LVPECL reference clock input LVPECL reference clock input. Weak pull-up to VDD/2.
PECL_CLK# I, PU/PD
LVCMOS LVCMOS/LVTTL reference clock input LVCMOS Clock output bank A LVCMOS Clock output bank B LVCMOS Clock output bank C LVCMOS Clock output bank D LVCMOS Feedback clock input. Connect to an output for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. LVCMOS Output enable/disable input. See Table 2. LVCMOS PLL enable/disable input. See Table 2. LVCMOS Reference select input. See Table 2. LVCMOS Frequency select input, Bank (A:D). See Table 2. VDD VDD VDD VDD VDD Ground Ground 2.5V or 3.3V Power supply for bank B output clock[2,3] 2.5V or 3.3V Power supply for bank C output clocks[2,3] 2.5V or 3.3V Power supply for bank D output clocks[2,3] 2.5V or 3.3V Power supply for PLL[2,3] 2.5V or 3.3V Power supply for core, inputs, and bank A output clock[2,3] Analog ground Common ground
10 31 32 3, 4, 5, 6 27 23 15, 19 1 11 7 13, 17, 21, 25, 29
OE# PLL_EN REF_SEL SEL(A:D) VDDQB VDDQC VDDQD AVDD VDD AVSS VSS
I, PD I, PU I, PD I, PD Supply Supply Supply Supply Supply Supply Supply
Table 1. Frequency Table Feedback Output Divider /2 /4 /8 Table 2. Function Table Control REF_SEL PLL_EN OE# SELA SELB SELC SELD Default 0 1 0 0 0 0 0 0 PCLK Bypass mode, PLL disabled. The input clock connects to the output dividers Outputs enabled / 2 (Bank A) / 4 (Bank B) / 4 (Bank C) / 4 (Bank D) TCLK PLL enabled. The VCO output connects to the output dividers Outputs disabled (three-state), VCO running at its minimum frequency / 4 (Bank A ) / 8 (Bank B) / 8 (Bank C) / 8 (Bank D) 1 VCO Input Clock * 2 Input Clock * 4 Input Clock * 8 Input Frequency Range (AVDD = 3.3V) 100 MHz to 200 MHz 50 MHz to 125 MHz 25 MHz to 62.5 MHz Input Frequency Range (AVDD = 2.5V) 100 MHz to 190MHz 50 MHz to 95MHz 25 MHz to 47.5MHz
Notes: 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1-F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD power supply pins.
Document #: 38-07475 Rev. *A
Page 2 of 8
CY29351
Absolute Maximum Conditions
Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch-up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Manufacturing test Functional Ripple Frequency < 100 kHz Non Functional Functional Functional Functional Functional 2000 10 Functional Relative to VSS Relative to VSS Condition Min. -0.3 2.375 -0.3 -0.3 - 200 - -65 -40 - 42 105 - Max. 5.5 3.465 VDD + 0.3 VDD + 0.3 VDD / 2 - 150 +150 +85 +150 Unit V V V V V mA mVp-p C C C C/W C/W Volts ppm
DC Electrical Specifications (VDD = 2.5V 5%, TA = -40C to +85C)
Parameter VIL VIH VPP VCMR VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage Common Mode Range[4] Output Voltage, Input Current, Low[5] Output Voltage, High[5] Low[6] Input Current, High[6] PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance Condition LVCMOS LVCMOS LVPECL LVPECL IOL = 15mA IOH = -15mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Outputs loaded @ 200 MHz Min. - 1.7 250 1.0 - 1.8 - - - - - - - 14 Typ. - - - - - - - - 5 - 180 210 4 18 Max. 0.7 VDD+0.3 1000 VDD - 0.6 0.6 - -100 100 10 7 - - - 22 pF Unit V V mV V V V A A mA mA mA
DC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C)
Parameter VIL VIH VPP VCMR VOL VOH Description Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage Common Mode Range[4] Output Voltage, Low[5] Condition LVCMOS LVCMOS LVPECL LVPECL IOL = 24 mA IOL = 12 mA Output Voltage, High[5] Min. - 2.0 250 1.0 - - Typ. - - - - - - Max. 0.8 VDD + 0.3 1000 VDD - 0.6 0.55 0.30 Unit V V mV V V
IOH = -24 mA 2.4 - - V Notes: 4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 5. Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 6. Inputs have pull-up or pull-down resistors that affect the input current. Document #: 38-07475 Rev. *A Page 3 of 8
CY29351
DC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C) (continued)
Parameter IIL IIH IDDA IDDQ IDD CIN ZOUT Parameter fVCO fin Description Input Current, Low[6] Input Current, High
[6]
Condition VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Outputs loaded @ 200 MHz
Min. - - - - - - - 12
[7]
Typ. - - 5 - 270 300 4 15
Max. -100 100 10 7 - - - 18
Unit A A mA mA mA pF
PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance
AC Electrical Specifications (VDD = 2.5V 5%, TA = -40C to +85C)
Description VCO Frequency Input Frequency /2 Feedback /4 Feedback /8 Feedback Condition
Min. 200 100 50 25 0 25 500 1.2 - 100 50 25 47.5 45 0.1 -100 -100 - - -
Typ. - - - - - - - - - - - - - - - - - - - - 2.2 0.85 0.6 - - - - 175 -
Max. 380 190 95 47.5 200 75 1000 VDD - 0.6 1.0 190 95 47.5 52.5 55 1.0 100 100 150 10 10 - - - 150 250 100 175 - 1
Unit MHz MHz
Bypass mode (PLL_EN = 0) frefDC VPP VCMR tr , tf fMAX Input Duty Cycle Peak-Peak Input Voltage Common Mode Range[8] TCLK Input Rise/FallTime Maximum Output Frequency LVPECL LVPECL 0.7V to 1.7V /2 Output /4 Output /8 Output DC tr , tf t() tsk(O) tPLZ, HZ tPZL, ZH BW Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time /2 Feedback /4 Feedback /8 Feedback tJIT(CC) tJIT(PER) tJIT() tLOCK Same frequency Multiple frequencies Same frequency Multiple frequencies fMAX < 100 MHz fMAX > 100 MHz 0.6V to 1.8V TCLK to FB_IN PCLK to FB_IN
% mV V ns MHz
% ns ps ps ns ns MHz
- - - - - - - - -
ps ps ps ms
Notes: 7. AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested. 8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Document #: 38-07475 Rev. *A
Page 4 of 8
CY29351
AC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C) [7]
Parameter fVCO fin Description VCO Frequency Input Frequency /2 Feedback /4 Feedback /8 Feedback Bypass mode (PLL_EN = 0) frefDC VPP VCMR tr , tf fMAX Input Duty Cycle Peak-Peak Input Voltage Common Mode Range[8] TCLK Input Rise/FallTime Maximum Output Frequency LVPECL LVPECL 0.8V to 2.0V /2 Output /4 Output /8 Output DC tr , tf t() tsk(O) tsk(B) tPLZ, HZ tPZL, ZH BW Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time
P u ls e G e n e ra to r Z = 50 ohm Zo = 50 ohm RT = 50 ohm
Condition
Min. 200 100 50 25 0 25 500 1.2 - 100 50 25 47.5 45 0.1 -100 -100 - - - -
Typ. - - - - - - - - - - - - - - - - - - - - - 2.2 0.85 0.6 - - - - 175 -
Max. 500 200 125 62.5 200 75 1000 VDD - 0.9 1.0 200 125 62.5 52.5 55 1.0 100 100 150 350 10 10 - - - 150 250 100 150 - 1
Unit MHz MHz
% mV V ns MHz
fMAX < 100 MHz fMAX > 100 MHz 0.8V to 2.4V TCLK to FB_IN, same VDD PCLK to FB_IN, same VDD Banks at same voltage Banks at different voltages
% ns ps ps ps ns ns MHz
/2 Feedback /4 Feedback /8 Feedback Same frequency Multiple frequencies Same frequency Multiple frequencies I/O same VDD
- - - - - - - - -
Zo = 50 ohm
tJIT(CC) tJIT(PER) tJIT() tLOCK
ps ps ps ms
RT = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK AC Test Reference for VDD = 3.3V / 2.5V
Zo = 50 ohm D iffe re n tia l P u ls e G e n e ra to r Z = 50 ohm Zo = 50 ohm Zo = 50 ohm R T = 50 ohm R T = 50 ohm
VTT
VTT
Figure 2. PECL_CLK AC Test Reference for VDD = 3.3V / 2.5V
Document #: 38-07475 Rev. *A
Page 5 of 8
CY29351
PECL_CLK PECL_CLK
VPP
VCMR
VDD
FB_IN
t()
VDD/2 GND
Figure 3. LVPECL Propagation Delay t(f), static phase offset
LVCMOS_CLK
VDD VDD/2 GND VDD
FB_IN
VDD/2
t()
GND
Figure 4. LVCMOS Propagation Delay t(), static phase offset
VDD
tP
T0
VDD/2 GND
DC = tP / T0 x 100%
Figure 5. Output Duty Cycle (DC)
VDD VDD/2 GND VDD VDD/2
tSK(O)
Figure 6. Output-to-Output Skew, tsk(O)
GND
Ordering Information
Part Number CY29351AI CY29351AIT 32-pin TQFP 32-pin TQFP - Tape and Reel Package Type Product Flow Industrial, -40C to +85C Industrial, -40C to 85C
Document #: 38-07475 Rev. *A
Page 6 of 8
CY29351
Package Drawing and Dimension
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
51-85088-*B
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07475 Rev. *A
Page 7 of 8
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY29351
Document History Page
Document Title:CY29351 2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer Document Number: 38-07475 REV. ** *A ECN No. 128152 245448 Issue Date 07/07/03 See ECN Orig. of Change RGL RGL New Data Sheet Re-worded Select Function Descriptions in table 2. Description of Change
Document #: 38-07475 Rev. *A
Page 8 of 8
WWW..COM
Copyright (c) Each Manufacturing Company. All Datasheets cannot be modified without permission.
This datasheet has been download from : www..com
100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www..com

▲Up To Search▲

Price & Availability of CY29351

	To Download CY29351 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .